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» Constraint-based model synthesis
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VLSID
1997
IEEE
98views VLSI» more  VLSID 1997»
15 years 6 months ago
Synthesis for Logical Initializability of Synchronous Finite State Machines
—Logical initializability is the property of a gate-level circuit whereby it can be driven to a unique start state when simulated by a three-valued (0, 1, ) simulator. In practic...
Montek Singh, Steven M. Nowick
ISSS
1996
IEEE
169views Hardware» more  ISSS 1996»
15 years 6 months ago
The Use of a Virtual Instruction Set for the Software Synthesis of HW/SW Embedded Systems
The application range of the embedded computing is going to cover the majority of the market products spanning from consumer electronic, automotive, telecom and process control. F...
Alessandro Balboni, William Fornaciari, M. Vincenz...
ENTCS
2006
109views more  ENTCS 2006»
15 years 1 months ago
Incremental Verification for On-the-Fly Controller Synthesis
The CIRCA system automatically synthesizes hard real-time discrete event controllers from plant and environment descriptions. CIRCA's automatically-synthesized controllers pr...
David J. Musliner, Michael J. S. Pelican, Robert P...
FPL
2003
Springer
95views Hardware» more  FPL 2003»
15 years 7 months ago
A Model for Hardware Realization of Kernel Loops
Abstract. Hardware realization of kernel loops holds the promise of accelerating the overall application performance and is therefore an important part of the synthesis process. In...
Jirong Liao, Weng-Fai Wong, Tulika Mitra
DATE
2003
IEEE
100views Hardware» more  DATE 2003»
15 years 7 months ago
Improving SAT-Based Bounded Model Checking by Means of BDD-Based Approximate Traversals
: Binary Decision Diagrams (BDDs) have been widely used in synthesis and verification. Boolean Satisfiability (SAT) Solvers, on the other hand, have been gaining
Gianpiero Cabodi, Sergio Nocco, Stefano Quer