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CHARME
2003
Springer
196views Hardware» more  CHARME 2003»
15 years 5 months ago
Analyzing the Intel Itanium Memory Ordering Rules Using Logic Programming and SAT
We present a non-operational approach to specifying and analyzing shared memory consistency models. The method uses higher order logic to capture a complete set of ordering constra...
Yue Yang, Ganesh Gopalakrishnan, Gary Lindstrom, K...
RTAS
2008
IEEE
15 years 6 months ago
Hybrid Timing Analysis of Modern Processor Pipelines via Hardware/Software Interactions
Embedded systems are often subject to constraints that require determinism to ensure that task deadlines are met. Such systems are referred to as real-time systems. Schedulability...
Sibin Mohan, Frank Mueller
ISCA
2010
IEEE
219views Hardware» more  ISCA 2010»
15 years 4 months ago
Using hardware vulnerability factors to enhance AVF analysis
Fault tolerance is now a primary design constraint for all major microprocessors. One step in determining a processor’s compliance to its failure rate target is measuring the Ar...
Vilas Sridharan, David R. Kaeli
EMSOFT
2009
Springer
15 years 6 months ago
Cache-aware scheduling and analysis for multicores
The major obstacle to use multicores for real-time applications is that we may not predict and provide any guarantee on real-time properties of embedded software on such platforms...
Nan Guan, Martin Stigge, Wang Yi, Ge Yu
STOC
2004
ACM
150views Algorithms» more  STOC 2004»
16 years 1 days ago
Typical properties of winners and losers in discrete optimization
We present a probabilistic analysis for a large class of combinatorial optimization problems containing, e.g., all binary optimization problems defined by linear constraints and a...
René Beier, Berthold Vöcking