1617 search results - page 295 / 324 » Constraints in Weighted Averaging |
120
Voted
DAC
2006
ACM
16 years 1 months ago
2006
ACM
Field programmable dual-Vdd interconnects are effective to reduce FPGA power. Assuming uniform length interconnects, existing work has developed time slack budgeting to minimize p...
115
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SIGSOFT
2003
ACM
16 years 1 months ago
2003
ACM
Memory corruption errors lead to non-deterministic, elusive crashes. This paper describes ARCHER (ARray CHeckER) a static, effective memory access checker. ARCHER uses path-sensit...
ICCAD
2007
IEEE
15 years 9 months ago
2007
IEEE
—This work proposes a new yield computation technique dedicated to HLS, which is an essential component in timing variationaware HLS research field. The SSTAs used by the curren...
ICCAD
2004
IEEE
15 years 9 months ago
2004
IEEE
In this paper we study the technology mapping problem for FPGA architectures to minimize chip area, or the total number of lookup tables (LUTs) of the mapped design, under the chi...
119
Voted
SARA
2009
Springer
15 years 7 months ago
2009
Springer
We study novel approaches for solving of hard combinatorial problems by translation to Boolean Satisfiability (SAT). Our focus is on combinatorial problems that can be represented...