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TII
2010
113views Education» more  TII 2010»
14 years 7 months ago
An Automated Framework for Formal Verification of Timed Continuous Petri Nets
In this paper, we develop an automated framework for formal verification of timed continuous Petri nets (ContPNs). Specifically, we consider two problems: (1) given an initial set ...
Marius Kloetzer, Cristian Mahulea, Calin Belta, Ma...
ISQED
2011
IEEE
230views Hardware» more  ISQED 2011»
14 years 4 months ago
Constraint generation for software-based post-silicon bug masking with scalable resynthesis technique for constraint optimizatio
Due to the dramatic increase in design complexity, verifying the functional correctness of a circuit is becoming more difficult. Therefore, bugs may escape all verification effo...
Chia-Wei Chang, Hong-Zu Chou, Kai-Hui Chang, Jie-H...
96
Voted
GLVLSI
2007
IEEE
194views VLSI» more  GLVLSI 2007»
15 years 4 months ago
Probabilistic maximum error modeling for unreliable logic circuits
Reliability modeling and evaluation is expected to be one of the major issues in emerging nano-devices and beyond 22nm CMOS. Such devices would have inherent propensity for gate f...
Karthikeyan Lingasubramanian, Sanjukta Bhanja
87
Voted
SDM
2007
SIAM
104views Data Mining» more  SDM 2007»
15 years 2 months ago
Boosting Optimal Logical Patterns Using Noisy Data
We consider the supervised learning of a binary classifier from noisy observations. We use smooth boosting to linearly combine abstaining hypotheses, each of which maps a subcube...
Noam Goldberg, Chung-chieh Shan
99
Voted
DATE
2009
IEEE
106views Hardware» more  DATE 2009»
15 years 7 months ago
Debugging of Toffoli networks
—Intensive research is performed to find post-CMOS technologies. A very promising direction based on reversible logic are quantum computers. While in the domain of reversible lo...
Robert Wille, Daniel Große, Stefan Frehse, G...