249 search results - page 11 / 50 » Context Sensitivity in Logical Modeling with Time Delays |
PDP
2009
IEEE
15 years 6 months ago
2009
IEEE
Existing approaches for modelling the Internet delay space predict end-to-end delays between two arbitrary hosts as static values. Further, they do not capture the characteristics...
ASPDAC
2008
ACM
15 years 1 months ago
2008
ACM
With continued scaling of technology into nanometer regimes, the impact of coupling induced delay variations is significant. While several coupling-aware static timers have been pr...
ISQED
2003
IEEE
15 years 5 months ago
2003
IEEE
A structurally testable delay fault might become untestable in the functional mode of the circuit due to logic or timing constraints or both. Experimental data suggests that there...
ICCD
1993
IEEE
15 years 3 months ago
1993
IEEE
Ravel-XL is a single-boardhardware accelerator for gate-level digital logic simulation. It uses a standard levelizedcode approach to statically schedule gate evaluations.However, u...
FPGA
1999
ACM
15 years 4 months ago
1999
ACM
In this paper, we investigate the speed and area-efficiency of FPGAs employing “logic clusters” containing multiple LUTs and registers as their logic block. We introduce a ne...