249 search results - page 16 / 50 » Context Sensitivity in Logical Modeling with Time Delays |
107
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PATMOS
2005
Springer
15 years 7 months ago
2005
Springer
The time taken for a CMOS logic gate output to change after one or more inputs have changed is called the output delay of the gate. A conventional multi-input CMOS gate is designed...
131
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CONTEXT
2003
Springer
15 years 7 months ago
2003
Springer
In conventional security systems, protected resources such as documents, hardware devices and software applications follow an On/Off access policy. On, allows to grant access and ...
92
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ICCAD
1992
IEEE
15 years 6 months ago
1992
IEEE
This paper presents a comprehensive timing model for behavioral-level specifications and algorithms for timing analysis in high-level synthesis. It is based on a timing network wh...
111
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ICCAD
2007
IEEE
15 years 10 months ago
2007
IEEE
While the increasing need for addressing process variability in sub-90nm VLSI technologies has sparkled a large body of statistical timing and optimization research, the realizati...
195
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Publication
Activity modelling and unusual event detection in a network of cameras is challenging particularly when the camera views are not overlapped. We show that it is possible to detect u...