249 search results - page 17 / 50 » Context Sensitivity in Logical Modeling with Time Delays |
105
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DATE
2006
IEEE
15 years 5 months ago
2006
IEEE
In this paper, we propose a timing-reasoning algorithm to improve the resolution of delay fault diagnosis. In contrast to previous approaches which identify candidates by utilizin...
101
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ICCD
2004
IEEE
15 years 8 months ago
2004
IEEE
Deterministic gate delay models have been widely used to find the transition probabilities at the nodes of a circuit for calculating the power dissipation. However, with progress...
AINA
2007
IEEE
15 years 6 months ago
2007
IEEE
In the near future, homes are envisioned to be equipped with numerous intelligent communicating devices. Such smart home needs to exhibit highly adaptive behavior to meet the inha...
DATE
2004
IEEE
15 years 3 months ago
2004
IEEE
Noise affects circuit operation by increasing gate delays and causing latches to capture incorrect values. Noise analysis techniques can detect some of such noise faults, but accu...
DATE
2006
IEEE
15 years 5 months ago
2006
IEEE
Abstract— Continuing scaling of CMOS technology has allowed aggressive pursuant of increased clock rate in DSM chips. The ever shorter clock period has made switching times of di...