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» Context Sensitivity in Logical Modeling with Time Delays
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FPGA
2007
ACM
142views FPGA» more  FPGA 2007»
15 years 6 months ago
Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis
Variations in the semiconductor fabrication process results in variability in parameters between transistors on the same die, a problem exacerbated by lithographic scaling. The re...
N. Pete Sedcole, Peter Y. K. Cheung
ISQED
2009
IEEE
126views Hardware» more  ISQED 2009»
15 years 6 months ago
Robust differential asynchronous nanoelectronic circuits
Abstract — Nanoelectronic design faces unprecedented reliability challenges and must achieve noise immunity and delay insensitiveness in the presence of prevalent defects and sig...
Bao Liu
TCS
2008
14 years 11 months ago
Temporal constraints in the logical analysis of regulatory networks
Starting from the logical description of gene regulatory networks developed by R. Thomas, we introduce an enhanced modelling approach based on timed automata. We obtain a refined ...
Heike Siebert, Alexander Bockmayr
IICS
2004
Springer
15 years 5 months ago
Towards Logical Hypertext Structure
Facing the retrieval problem according to the overwhelming set of documents online the adaptation of text categorization to web units has recently been pushed. The aim is to utiliz...
Alexander Mehler, Matthias Dehmer, Rüdiger Gl...
JCDL
2009
ACM
130views Education» more  JCDL 2009»
15 years 6 months ago
Whetting the appetite of scientists: producing summaries tailored to the citation context
The amount of scientific material available electronically is forever increasing. This makes reading the published literature, whether to stay up-to-date on a topic or to get up ...
Stephen Wan, Cécile Paris, Robert Dale