249 search results - page 7 / 50 » Context Sensitivity in Logical Modeling with Time Delays |
105
Voted
SOCINFO
2010
14 years 8 months ago
2010
Abstract. Online tools for collaboration and social platforms have become omnipresent in Web-based environments. Interests and skills of people evolve over time depending in perfor...
EOR
2010
14 years 9 months ago
2010
Resources including various assets of supply chains, face random demand over time and can be shared by others. We consider an operational setting where a resource is shared by two...
88
Voted
ASPDAC
2006
ACM
15 years 3 months ago
2006
ACM
- One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology ta...
DAC
2008
ACM
15 years 10 months ago
2008
ACM
Many recent techniques for timing analysis under variability, in which delay is an explicit function of underlying parameters, may be described as parameterized timing analysis. T...
81
Voted
ISPD
2003
ACM
15 years 2 months ago
2003
ACM
Delay evaluation is always a crucial concern in the VLSI design and it becomes increasingly more critical in the nowadays deep-submicron technology. To obtain an accurate delay va...