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» Context Sensitivity in Logical Modeling with Time Delays
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ISQED
2003
IEEE
102views Hardware» more  ISQED 2003»
15 years 2 months ago
Modeling Crosstalk Induced Delay
The amplitude of coupled noise is often used in estimating the crosstalk effect. Coupling noise-induced delay measures the impact of crosstalk on circuit performance. Efficient c...
Chung-Kuan Tsai, Malgorzata Marek-Sadowska
83
Voted
DAC
1995
ACM
15 years 1 months ago
Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization
Abstract—With delays due to the physical interconnect dominating the overall logic path delays, circuit-level delay optimization must take interconnect effects into account. Inst...
Noel Menezes, Satyamurthy Pullela, Lawrence T. Pil...
81
Voted
DAC
2004
ACM
15 years 1 months ago
Statistical gate delay model considering multiple input switching
There is an increased dominance of intra-die process variations, creating a need for an accurate and fast statistical timing analysis. Most of the recent proposed approaches assum...
Aseem Agarwal, Florentin Dartu, David Blaauw
91
Voted
ICCAD
1995
IEEE
134views Hardware» more  ICCAD 1995»
15 years 1 months ago
A delay model for logic synthesis of continuously-sized networks
ng certain electrical noise and power constraints.Abstract: We present a new delay model for use in logic synthesis. A traditional model treats the area of a library cell as consta...
Joel Grodstein, Eric Lehman, Heather Harkness, Bil...
VTC
2007
IEEE
103views Communications» more  VTC 2007»
15 years 3 months ago
On the Problems of Symbol-Spaced Tapped-Delay-Line Models for WSSUS Channels
—This paper reviews the pertinence and statistical behavior of symbol-spaced tapped-delay-line (TDL) models which are widely used to model wide-sense stationary uncorrelated scat...
Carlos A. Gutiérrez-Díaz-de-Le&oacut...