Sciweavers

249 search results - page 9 / 50
» Context Sensitivity in Logical Modeling with Time Delays
Sort
View
ISQED
2009
IEEE
187views Hardware» more  ISQED 2009»
15 years 6 months ago
An efficient current-based logic cell model for crosstalk delay analysis
 Electrical Modeling for High Bandwidth IO Link  Chirayu Amin, Chandramouli Kashyap ¬ Intel Corp., Hillsboro, OR  Prateek Bhansali ¬ Univ. of Minnesota, Mi...
Debasish Das, William Scott, Shahin Nazarian, Hai ...
VLSID
1999
IEEE
93views VLSI» more  VLSID 1999»
15 years 4 months ago
Spec-Based Repeater Insertion and Wire Sizing for On-chip Interconnect
Recently Lillis, et al. presented an elegant dynamic programming approach to RC interconnect delay optimization through driver sizing, repeater insertion, and, wire sizing which e...
Noel Menezes, Chung-Ping Chen
SODA
2008
ACM
124views Algorithms» more  SODA 2008»
15 years 1 months ago
Competitive queue management for latency sensitive packets
We consider the online problem of non-preemptive queue management. An online sequence of packets arrive, each of which has an associated intrinsic value. Packets can be accepted t...
Amos Fiat, Yishay Mansour, Uri Nadav
ITC
2003
IEEE
167views Hardware» more  ITC 2003»
15 years 5 months ago
Path Delay Test Generation for Domino Logic Circuits in the Presence of Crosstalk
A technique to derive test vectors that exercise the worstcase delay effects in a domino circuit in the presence of crosstalk is described. A model for characterizing the delay of...
Rahul Kundu, R. D. (Shawn) Blanton
LICS
1991
IEEE
15 years 3 months ago
Logic Programming in a Fragment of Intuitionistic Linear Logic
When logic programming is based on the proof theory of intuitionistic logic, it is natural to allow implications in goals and in the bodies of clauses. Attempting to prove a goal ...
Joshua S. Hodas, Dale Miller