Sciweavers

677 search results - page 47 / 136
» Context-Aware Performance Analysis for Efficient Embedded Sy...
Sort
View
CODES
1999
IEEE
15 years 5 months ago
An MPEG-2 decoder case study as a driver for a system level design methodology
We present a case study on the design of a heterogeneous architecture for MPEG-2 video decoding. The primary objective of the case study is the validation of the SPADE methodology...
Pieter van der Wolf, Paul Lieverse, Mudit Goel, Da...
CODES
2001
IEEE
15 years 5 months ago
Towards effective embedded processors in codesigns: customizable partitioned caches
This paper explores an application-specific customization technique for the data cache, one of the foremost area/power consuming and performance determining microarchitectural fea...
Peter Petrov, Alex Orailoglu
CODES
2008
IEEE
15 years 3 months ago
Performance debugging of Esterel specifications
Synchronous languages like Esterel have been widely adopted for designing reactive systems in safety-critical domains such as avionics. Specifications written in Esterel are based...
Lei Ju, Bach Khoa Huynh, Abhik Roychoudhury, Samar...
CODES
2008
IEEE
15 years 7 months ago
Intra- and inter-processor hybrid performance modeling for MPSoC architectures
The heterogeneity of modern MPSoC architectures, coupled with the increasing complexity of the applications mapped onto them has recently led to a lot of interest in hybrid perfor...
Frank E. B. Ophelders, Samarjit Chakraborty, Henk ...
DATE
2007
IEEE
92views Hardware» more  DATE 2007»
15 years 7 months ago
Overcoming glitches and dissipation timing skews in design of DPA-resistant cryptographic hardware
Cryptographic embedded systems are vulnerable to Differential Power Analysis (DPA) attacks. In this paper, we propose a logic design style, called as Precharge Masked Reed-Muller ...
Kuan Jen Lin, Shan Chien Fang, Shih Hsien Yang, Ch...