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ISLPED
1995
ACM
114views Hardware» more  ISLPED 1995»
15 years 1 months ago
Power and area optimization by reorganizing CMOS complex gate circuits
Thispaper proposes a method for achieving low-power control-logic modules using a combination of CMOS complex gate reorganization, transistor size optimization, and transistor lay...
M. Tachibana, S. Kurosawa, R. Nojima, Norman Kojim...
AUSDM
2008
Springer
246views Data Mining» more  AUSDM 2008»
14 years 12 months ago
A New Evaluation Measure for Imbalanced Datasets
The area of imbalanced datasets is still relatively new, and it is known that the use of overall accuracy is not an appropriate evaluation measure for imbalanced datasets, because...
Cheng G. Weng, Josiah Poon
DAC
2005
ACM
14 years 11 months ago
Multiplexer restructuring for FPGA implementation cost reduction
This paper presents a novel synthesis algorithm that reduces the area needed for implementing multiplexers on an FPGA by an average of 18%. This is achieved by reducing the number...
Paul Metzgen, Dominic Nancekievill
ECAI
2008
Springer
14 years 11 months ago
An Analysis of Bayesian Network Model-Approximation Techniques
Abstract. Two approaches have been used to perform approximate inference in Bayesian networks for which exact inference is infeasible: employing an approximation algorithm, or appr...
Adamo Santana, Gregory M. Provan
FPL
2008
Springer
129views Hardware» more  FPL 2008»
14 years 11 months ago
Power reduction techniques for Dynamically Reconfigurable Processor Arrays
The power consumption of Dynamically Reconfigurable Processing Array (DRPA) is quantitatively analyzed by using a real chip layout and applications taking into account the reconfi...
Takashi Nishimura, Keiichiro Hirai, Yoshiki Saito,...