443 search results - page 35 / 89 » Continual flow pipelines |
ICIP
2007
IEEE
16 years 3 months ago
2007
IEEE
The in-loop deblocking filter contains highly adaptive processing on both sample level and block edge level, which inevitably appears in the loop kernel of the algorithm. Therefor...
101
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DAC
2003
ACM
16 years 2 months ago
2003
ACM
Many embedded systems use a simple pipelined RISC processor for computation and an on-chip SRAM for data storage. We present an enhancement called Intelligent SRAM (ISRAM) that co...
101
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DAC
2005
ACM
16 years 2 months ago
2005
ACM
The increased deployment of System-on-Chip designs has drawn attention to the limitations of on-chip interconnects. As a potential solution to these limitations, Networks-on -Chip...
138
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ESTIMEDIA
2005
Springer
15 years 7 months ago
2005
Springer
Designing Application-Specific Instruction-set Processors (ASIPs) usually requires designing a custom datapath, and modifying instruction-set, instruction decoder, and compiler. A...
111
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CHES
2006
Springer
15 years 5 months ago
2006
Springer
Balanced dynamic dual-rail gates and asynchronous circuits have been shown, if implemented correctly, to have natural and efficient resistance to side-channel attacks. Despite thei...