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109
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DATE
2006
IEEE
66views Hardware» more  DATE 2006»
15 years 8 months ago
Power/performance hardware optimization for synchronization intensive applications in MPSoCs
This paper explores optimization techniques of the synchronization mechanisms for MPSoCs based on complex interconnect (Network-on-Chip), targeted at future powerefficient system...
Matteo Monchiero, Gianluca Palermo, Cristina Silva...
146
Voted
ASPDAC
2005
ACM
193views Hardware» more  ASPDAC 2005»
15 years 8 months ago
VLSI on-chip power/ground network optimization considering decap leakage currents
- In today’s power/ground(P/G) network design, on-chip decoupling capacitors(decaps) are usually made of MOS transistors with source and drain connected together. The gate leak...
Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, ...
108
Voted
FOCS
2004
IEEE
15 years 6 months ago
Optimal Power-Down Strategies
We consider the problem of selecting threshold times to transition a device to low-power sleep states during an idle period. The two-state case in which there is a single active a...
John Augustine, Sandy Irani, Chaitanya Swamy
142
Voted
WSC
2007
15 years 5 months ago
Allocation of simulation runs for simulation optimization
Simulation optimization (SO) is the process of finding the optimum design of a system whose performance measure(s) are estimated via simulation. We propose some ideas to improve o...
Alireza Kabirian, Sigurdur Ólafsson
IIS
2000
15 years 4 months ago
Optimization and Interpretation of Rule-based Classifiers
Machine learning methods are frequently used to create rule-based classifiers. For continuous features linguistic variables used in conditions of the rules are defined by membershi...
Wlodzislaw Duch, Norbert Jankowski, Krzysztof Grab...