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CODES
2006
IEEE
15 years 9 months ago
Yield prediction for architecture exploration in nanometer technology nodes: : a model and case study for memory organizations
Process variability has a detrimental impact on the performance of memories and other system components, which can lead to parametric yield loss at the system level due to timing ...
Antonis Papanikolaou, T. Grabner, Miguel Miranda, ...
DATE
2010
IEEE
156views Hardware» more  DATE 2010»
15 years 8 months ago
Domain specific architecture for next generation wireless communication
—In order to solve the challenges in processor design for the next generation wireless communication systems, this paper first proposes a system level design flow for communicati...
Botao Zhang, Hengzhu Liu, Heng Zhao, Fangzheng Mo,...
LCTRTS
2000
Springer
15 years 6 months ago
Reordering Memory Bus Transactions for Reduced Power Consumption
Low energy consumption is becoming the primary design consideration for battery-operated and portable embedded systems, such as personal digital assistants, digital still and movi...
Bruce R. Childers, Tarun Nakra
PPAM
2007
Springer
15 years 9 months ago
Using HLA and Grid for Distributed Multiscale Simulations
Combining simulations of different scale in one application is non-trivial issue. This paper proposes solution that supports complex time interactions that can appear between elem...
Katarzyna Rycerz, Marian Bubak, Peter M. A. Sloot
DATE
2006
IEEE
112views Hardware» more  DATE 2006»
15 years 9 months ago
On the verification of automotive protocols
Verification quality is a must for functional safety in electronic systems. In automotive, the verification flow is historically based on a layered approach, where each level (mod...
G. Zarri, F. Colucci, F. Dupuis, R. Mariani, M. Pa...