Traditionally, synchronous languages, such as Esterel, have been compiled into hardware, where timing analysis is relatively easy. When compiled into software ? e.g., into sequent...
Lei Ju, Bach Khoa Huynh, Samarjit Chakraborty, Abh...
A very long instruction word (VLIW) processorexploits parallelism by controlling multiple operations in a single instruction word. This paper describes the architecture and compil...
Robert Cohn, Thomas R. Gross, Monica S. Lam, P. S....
Abstract. On multi-core architectures with software-managed memories, effectively orchestrating data movement is essential to performance, but is tedious and error-prone. In this p...
Lee W. Howes, Anton Lokhmotov, Alastair F. Donalds...
Software frameworks impose constraints on how plugins may interact with them. Many of hese constraints involve multiple objects, are temporal, and depend on runtime values. Additi...
A modeling process is presented for extracting timingaccurate simulation models from complex embedded realtime systems. The process is supported by two complementary methods for t...
Johan Andersson, Joel Huselius, Christer Norstr&ou...