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DFT
2003
IEEE
113views VLSI» more  DFT 2003»
15 years 9 months ago
Buffer and Controller Minimisation for Time-Constrained Testing of System-On-Chip
Test scheduling and Test Access Mechanism (TAM) design are two important tasks in the development of a System-on-Chip (SOC) test solution. Previous test scheduling techniques assu...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...
FTDCS
2003
IEEE
15 years 9 months ago
A System Architecture for Distributed Control Loop Applications
Umakishore Ramachandran, Phillip W. Hutto, Bikash ...