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» Control network generator for latency insensitive designs
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NOCS
2007
IEEE
15 years 3 months ago
On the Design of a Photonic Network-on-Chip
Recent remarkable advances in nanoscale siliconphotonic integrated circuitry specifically compatible with CMOS fabrication have generated new opportunities for leveraging the uni...
Assaf Shacham, Keren Bergman, Luca P. Carloni
ACMSE
2007
ACM
15 years 1 months ago
Minimizing broadcast latency in ad hoc wireless networks
Network wide broadcasting in ad-hoc wireless networks provides important control and route establishment functionality for a number of unicast and multicast protocols. In broadcas...
Shankar M. Banik, Sridhar Radhakrishnan
HOTNETS
2010
14 years 4 months ago
Next generation on-chip networks: what kind of congestion control do we need?
In this paper, we present network-on-chip (NoC) design and contrast it to traditional network design, highlighting core differences between NoCs and traditional networks. As an in...
George Nychis, Chris Fallin, Thomas Moscibroda, On...
DAC
2005
ACM
15 years 10 months ago
A low latency router supporting adaptivity for on-chip interconnects
The increased deployment of System-on-Chip designs has drawn attention to the limitations of on-chip interconnects. As a potential solution to these limitations, Networks-on -Chip...
Jongman Kim, Dongkook Park, Theo Theocharides, Nar...
MSWIM
2005
ACM
15 years 3 months ago
Latency-sensitive power control for wireless ad-hoc networks
We investigate the impact of power control on latency in wireless ad-hoc networks. If transmission power is increased, interference increases, thus reducing network capacity. A no...
Mohamed R. Fouad, Sonia Fahmy, Gopal Pandurangan