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» Control network generator for latency insensitive designs
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SBCCI
2005
ACM
114views VLSI» more  SBCCI 2005»
15 years 3 months ago
Traffic generation and performance evaluation for mesh-based NoCs
The designer of a system on a chip (SoC) that connects IP cores through a network on chip (NoC) needs methods to support application performance evaluation. Two key aspects these ...
Leonel Tedesco, Aline Mello, Diego Garibotti, Ney ...
ICRA
2005
IEEE
155views Robotics» more  ICRA 2005»
15 years 3 months ago
CPG Design using Inhibitory Networks
– We describe in detail the behavior of an inhibitory Central Pattern Generator (CPG) network for robot control. A four-neuron, mutual inhibitory network forms the basic coordina...
M. Anthony Lewis, Francesco Tenore, Ralph Etienne-...
NETGAMES
2004
ACM
15 years 3 months ago
Some thoughts on emulating jitter for user experience trials
It is usually hard to control the network conditions affecting public online game servers when studying the impact of latency, loss and jitter on user experience. This leads to a ...
Grenville J. Armitage, Lawrence Stewart
SASO
2008
IEEE
15 years 4 months ago
Aspects of Distance Sensitive Design of Wireless Sensor Networks
—Distance sensitivity is a locality concept that is useful for designing scalable wireless sensor network applications. In this paper, we formally define distance sensitivity an...
Vinod Kulathumani, Anish Arora
ICCAD
2008
IEEE
80views Hardware» more  ICCAD 2008»
15 years 6 months ago
Advancing supercomputer performance through interconnection topology synthesis
—In today’s many-core era, the interconnection networks have been the key factor that dominates the performance of a computer system. In this paper, we propose a design flow t...
Yi Zhu, Michael Taylor, Scott B. Baden, Chung-Kuan...