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DATE
2000
IEEE
88views Hardware» more  DATE 2000»
15 years 5 months ago
Techniques for Reducing Read Latency of Core Bus Wrappers
Today’s system-on-a-chip designs consist of many cores. To enable cores to be easily integrated into different systems, many propose creating cores with their internal logic sep...
Roman L. Lysecky, Frank Vahid, Tony Givargis
WSC
2008
15 years 3 months ago
PLCStudio: Simulation based PLC code verification
Proposed in this paper is the architecture of a PLC programming environment that enables a visual verification of PLC programs. The proposed architecture integrates a PLC program ...
Sang C. Park, Chang Mok Park, Gi-Nam Wang, Jonggeu...
WSCG
2004
172views more  WSCG 2004»
15 years 2 months ago
GDESK: Game Discrete Event Simulation Kernel
Simulation has been used traditionally to solve other areas problems. Real time applications like videogames use typically a continuous simulation scheme. That way of operation ha...
Inmaculada García, Ramón Mollá...
SIGCOMM
2012
ACM
13 years 3 months ago
Bulk of interest: performance measurement of content-centric routing
The paradigm of information-centric networking subsumes recent approaches to integrate content replication services into a future Internet layer. Current concepts foster either a ...
Matthias Wählisch, Thomas C. Schmidt, Markus ...
HASE
2007
IEEE
15 years 7 months ago
Analytic Model for Web Anomalies Classification
In this paper, an analytic technique is proposed to improve the dynamic web application quality and reliability. The technique integrates orthogonal defect classification (ODC), a...
Nasser Alaeddine, Jeff Tian