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DAC
2010
ACM
15 years 1 months ago
Eyecharts: constructive benchmarking of gate sizing heuristics
—Discrete gate sizing is one of the most commonly used, flexible, and powerful techniques for digital circuit optimization. The underlying problem has been proven to be NP-hard ...
Puneet Gupta, Andrew B. Kahng, Amarnath Kasibhatla...
TRIDENTCOM
2006
IEEE
15 years 3 months ago
QUETZAL: qualified ultra-wideband testbed for reduced data-rates and location
— This work presents an UWB testbed for reduced data rates with capabilities of measuring range and location. The transmitter uses Time Hopping spread spectrum codes to reduce th...
Antonio Mollfulleda, M. Nájar, P. Miskovsky...
MICRO
2008
IEEE
72views Hardware» more  MICRO 2008»
15 years 3 months ago
Low-power, high-performance analog neural branch prediction
Shrinking transistor sizes and a trend toward low-power processors have caused increased leakage, high per-device variation and a larger number of hard and soft errors. Maintainin...
Renée St. Amant, Daniel A. Jiménez, ...
ICCAD
2003
IEEE
132views Hardware» more  ICCAD 2003»
15 years 6 months ago
A Sum-over-Paths Impulse-Response Moment-Extraction Algorithm for IC-Interconnect Networks: Verification, Coupled RC Lines
We have created a stochastic impulse-response (IR) momentextraction algorithm for RC circuit networks. It employs a newly discovered Feynman Sum-over-Paths Postulate. Full paralle...
Yannick L. Le Coz, Dhivya Krishna, Dusan M. Petran...
ICCAD
2005
IEEE
107views Hardware» more  ICCAD 2005»
15 years 6 months ago
Projection-based performance modeling for inter/intra-die variations
Large-scale process fluctuations in nano-scale IC technologies suggest applying high-order (e.g., quadratic) response surface models to capture the circuit performance variations....
Xin Li, Jiayong Le, Lawrence T. Pileggi, Andrzej J...