74 search results - page 10 / 15 » Controlling Peak Power During Scan Testing |
DAC
2005
ACM
14 years 11 months ago
2005
ACM
This paper presents a new method for designing test wrappers for embedded cores with multiple clock domains. By exploiting the use of multiple shift frequencies, the proposed meth...
64
Voted
ITC
1999
IEEE
15 years 1 months ago
1999
IEEE
Power consumption of digital systems may increase significantly during testing. In this paper, systems equipped with a scan-based built-in self-test like the STUMPS architecture a...
DATE
2006
IEEE
15 years 3 months ago
2006
IEEE
In this paper we analyze the test power of SRAM memories and demonstrate that the full functional precharge activity is not necessary during test mode because of the predictable a...
DFT
2003
IEEE
15 years 2 months ago
2003
IEEE
For system-on-chip designs that contain an embedded processor, this paper present a software based diagnosis scheme that can make use of the processor to aid in diagnosis in a sca...
HAPTICS
2007
IEEE
15 years 3 months ago
2007
IEEE
The objective of the present research was to show that incorporating a visuo-haptic device ‘Telemaque’ may increase the fluency of handwriting production of cursive letters in...