74 search results - page 7 / 15 » Controlling Peak Power During Scan Testing |
DATE
2005
IEEE
15 years 3 months ago
2005
IEEE
— With increasing process fluctuations in nano-scale technology, testing for delay faults is becoming essential in manufacturing test to complement stuck-at-fault testing. Desig...
ICCD
2004
IEEE
15 years 6 months ago
2004
IEEE
— Reduction in test power is important to improve battery life in portable devices employing periodic self-test, to increase reliability of testing and to reduce test-cost. In sc...
121
Voted
DFT
2005
IEEE
14 years 11 months ago
2005
IEEE
A built-in self-test (BIST) scheme is presented which both reduces overhead for detecting random-pattern-resistant (r.p.r.) faults as well as reduces power consumption during test...
105
click to vote
DFT
2002
IEEE
15 years 2 months ago
2002
IEEE
Conversion of the flip-flops of the circuit into scan cells helps ease the test challenge; yet test application time is increased as serial shift operations are employed. Furthe...
85
Voted
ATS
2004
IEEE
15 years 1 months ago
2004
IEEE
In this paper, we propose a low-power testing methodology for the scan-based BIST. A smoother is included in the test pattern generator (TPG) to reduce average power consumption d...