160 search results - page 10 / 32 » Cooperative Caching for Chip Multiprocessors |
173
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ICCD
2011
IEEE
14 years 1 months ago
2011
IEEE
—A key challenge in chip multiprocessor (CMP) design is to optimize the performance within a power budget limited by the CMP’s cooling, packaging, and power supply capacities. ...
107
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ICCD
2007
IEEE
15 years 5 months ago
2007
IEEE
This paper presents a novel power reduction method for chip multi-processors (CMPs) under real-time constraints. While the power consumption of processing units (PUs) on CMPs can ...
111
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PPOPP
2009
ACM
16 years 2 months ago
2009
ACM
Data prefetching has been widely used in the past as a technique for hiding memory access latencies. However, data prefetching in multi-threaded applications running on chip multi...
120
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HPCC
2005
Springer
15 years 7 months ago
2005
Springer
In this paper we present an exhaustive evaluation of the memory subsystem in a chip-multiprocessor (CMP) architecture composed of 16 cores. The characterization is performed making...
MICRO
2010
IEEE
14 years 11 months ago
2010
IEEE
Efficient management of last level caches (LLCs) plays an important role in bridging the performance gap between processor cores and main memory. This paper is motivated by two key...