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» Cooperative Caching for Chip Multiprocessors
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ISCA
2007
IEEE
126views Hardware» more  ISCA 2007»
15 years 8 months ago
Comparing memory systems for chip multiprocessors
There are two basic models for the on-chip memory in CMP systems: hardware-managed coherent caches and software-managed streaming memory. This paper performs a direct comparison o...
Jacob Leverich, Hideho Arakida, Alex Solomatnikov,...
EUROPAR
2008
Springer
15 years 3 months ago
Exploration of the Influence of Program Inputs on CMP Co-scheduling
Recent studies have showed the effectiveness of job co-scheduling in alleviating shared-cache contention on Chip Multiprocessors. Although program inputs affect cache usage and thu...
Yunlian Jiang, Xipeng Shen
ISCA
2006
IEEE
162views Hardware» more  ISCA 2006»
15 years 7 months ago
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory
Long interconnects are becoming an increasingly important problem from both power and performance perspectives. This motivates designers to adopt on-chip network-based communicati...
Feihui Li, Chrysostomos Nicopoulos, Thomas D. Rich...
IEEEPACT
2008
IEEE
15 years 8 months ago
Improving support for locality and fine-grain sharing in chip multiprocessors
Both commercial and scientific workloads benefit from concurrency and exhibit data sharing across threads/processes. The resulting sharing patterns are often fine-grain, with t...
Hemayet Hossain, Sandhya Dwarkadas, Michael C. Hua...
CC
2010
Springer
190views System Software» more  CC 2010»
15 years 8 months ago
Is Reuse Distance Applicable to Data Locality Analysis on Chip Multiprocessors?
On Chip Multiprocessors (CMP), it is common that multiple cores share certain levels of cache. The sharing increases the contention in cache and memory-to-chip bandwidth, further h...
Yunlian Jiang, Eddy Z. Zhang, Kai Tian, Xipeng She...