Sciweavers

160 search results - page 13 / 32
» Cooperative Caching for Chip Multiprocessors
Sort
View
EUROSYS
2007
ACM
15 years 11 months ago
Thread clustering: sharing-aware scheduling on SMP-CMP-SMT multiprocessors
The major chip manufacturers have all introduced chip multiprocessing (CMP) and simultaneous multithreading (SMT) technology into their processing units. As a result, even low-end...
David K. Tam, Reza Azimi, Michael Stumm
DAMON
2007
Springer
15 years 8 months ago
Parallel buffers for chip multiprocessors
Chip multiprocessors (CMPs) present new opportunities for improving database performance on large queries. Because CMPs often share execution, cache, or bandwidth resources among ...
John Cieslewicz, Kenneth A. Ross, Ioannis Giannaka...
DAMON
2008
Springer
15 years 3 months ago
Data partitioning on chip multiprocessors
Partitioning is a key database task. In this paper we explore partitioning performance on a chip multiprocessor (CMP) that provides a relatively high degree of on-chip thread-leve...
John Cieslewicz, Kenneth A. Ross
128
Voted
ASAP
2005
IEEE
182views Hardware» more  ASAP 2005»
15 years 7 months ago
A Thread and Data-Parallel MPEG-4 Video Encoder for a System-On-Chip Multiprocessor
We studied the dynamic instruction count reduction for a single-thread, vectorized and a multi-threaded, non-vectorized, MPEG-4 video encoder. Results indicate a maximum improveme...
Tom R. Jacobs, José L. Núñez-...
129
Voted
IPPS
2006
IEEE
15 years 7 months ago
Reducing the associativity and size of step caches in CRCW operation
Step caches are caches in which data entered to an cache array is kept valid only until the end of ongoing step of execution. Together with an advanced pipelined multithreaded arc...
M. Forsell