Sciweavers

160 search results - page 22 / 32
» Cooperative Caching for Chip Multiprocessors
Sort
View
176
Voted
CAL
2008
15 years 1 months ago
BENoC: A Bus-Enhanced Network on-Chip for a Power Efficient CMP
Network-on-Chips (NoCs) outperform buses in terms of scalability, parallelism and system modularity and therefore are considered as the main interconnect infrastructure in future c...
I. Walter, Israel Cidon, Avinoam Kolodny
ISCA
2008
IEEE
114views Hardware» more  ISCA 2008»
15 years 8 months ago
Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks
Future chip multiprocessors (CMPs) may have hundreds to thousands of threads competing to access shared resources, and will require quality-of-service (QoS) support to improve sys...
Jae W. Lee, Man Cheuk Ng, Krste Asanovic
116
Voted
ISPASS
2010
IEEE
15 years 8 months ago
Cache contention and application performance prediction for multi-core systems
—The ongoing move to chip multiprocessors (CMPs) permits greater sharing of last-level cache by processor cores but this sharing aggravates the cache contention problem, potentia...
Chi Xu, Xi Chen, Robert P. Dick, Zhuoqing Morley M...
HPCA
2000
IEEE
15 years 6 months ago
Impact of Chip-Level Integration on Performance of OLTP Workloads
With increasing chip densities, future microprocessor designs have the opportunity to integrate many of the traditional systemlevel modules onto the same chip as the processor. So...
Luiz André Barroso, Kourosh Gharachorloo, A...
DELTA
2008
IEEE
15 years 3 months ago
Dynamic Co-operative Intelligent Memory
As semiconductor technology advances, the performance gap between processor and memory has become one of the major issues in computer design. In order to bridge this gap, many met...
Xiaoyong Wen, Faycal Bensaali, Reza Sotudeh