160 search results - page 27 / 32 » Cooperative Caching for Chip Multiprocessors |
236
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GLVLSI
2011
IEEE
14 years 5 months ago
2011
IEEE
This paper proposes a novel L1 data cache design with dualversioning SRAM cells (dvSRAM) for chip multi-processors (CMP) that implement optimistic concurrency proposals. In this n...
130
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DATE
2005
IEEE
15 years 7 months ago
2005
IEEE
Run-time task migration in a heterogeneous multiprocessor System-on-Chip (MP-SoC) is a challenge that requires cooperation between the task and the operating system. In task migra...
102
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ISCA
2005
IEEE
15 years 7 months ago
2005
IEEE
Chip multiprocessors (CMPs) substantially increase capacity pressure on the on-chip memory hierarchy while requiring fast access. Neither private nor shared caches can provide bot...
106
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HPCA
2006
IEEE
16 years 2 months ago
2006
IEEE
This paper explores the multi-dimensional design space for chip multiprocessors, exploring the inter-related variables of core count, pipeline depth, superscalar width, L2 cache s...
114
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HPCA
2003
IEEE
16 years 2 months ago
2003
IEEE
This paper identifies node affinity as an important property for scalable general-purpose locks. Nonuniform communication architectures (NUCAs), for example CCNUMAs built from a f...