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» Coordinated resource optimization in behavioral synthesis
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VLSID
2009
IEEE
155views VLSI» more  VLSID 2009»
15 years 10 months ago
Unified Challenges in Nano-CMOS High-Level Synthesis
: The challenges in nano-CMOS circuit design include the following: variability, leakage, power, thermals, reliability, and yield. This talk will focus on interdependent considerat...
Saraju P. Mohanty
ICCAD
2006
IEEE
131views Hardware» more  ICCAD 2006»
15 years 6 months ago
High-level synthesis challenges and solutions for a dynamically reconfigurable processor
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, T...
ICCAD
2009
IEEE
179views Hardware» more  ICCAD 2009»
14 years 7 months ago
Automatic memory partitioning and scheduling for throughput and power optimization
Hardware acceleration is crucial in modern embedded system design to meet the explosive demands on performance and cost. Selected computation kernels for acceleration are usually ...
Jason Cong, Wei Jiang, Bin Liu, Yi Zou
DSD
2010
IEEE
137views Hardware» more  DSD 2010»
14 years 7 months ago
A C-to-RTL Flow as an Energy Efficient Alternative to Embedded Processors in Digital Systems
We present a high-level synthesis flow for mapping an algorithm description (in C) to a provably equivalent registertransfer level (RTL) description of hardware. This flow uses an ...
Sameer D. Sahasrabuddhe, Sreenivas Subramanian, Ku...
CASES
2009
ACM
15 years 4 months ago
A platform for developing adaptable multicore applications
Computer systems are resource constrained. Application adaptation is a useful way to optimize system resource usage while satisfying the application performance constraints. Previ...
Dan Fay, Li Shang, Dirk Grunwald