131 search results - page 19 / 27 » Copy Elimination for Parallelizing Compilers |
100
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CF
2006
ACM
14 years 11 months ago
2006
ACM
The growing speed gap between memory and processor makes an efficient use of the cache ever more important to reach high performance. One of the most important ways to improve cac...
CGO
2010
IEEE
15 years 4 months ago
2010
IEEE
Tiling is a widely used loop transformation for exposing/exploiting parallelism and data locality. Effective use of tiling requires selection and tuning of the tile sizes. This is...
113
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IEEEPACT
2002
IEEE
15 years 2 months ago
2002
IEEE
Many modern embedded processors (esp. DSPs) support partitioned memory banks (also called X-Y memory or dual bank memory) along with parallel load/store instructions to achieve co...
CJ
2006
14 years 9 months ago
2006
Most microprocessor chips today use an out-of-order instruction execution mechanism. This mechanism allows superscalar processors to extract reasonably high levels of instruction ...
108
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ISCA
1995
IEEE
15 years 1 months ago
1995
IEEE
Communicationin aparallel systemfrequently involvesmoving data from the memory of one node to the memory of another; this is the standard communication model employedin message pa...