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» Core Algorithms of the Maui Scheduler
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ISSS
1995
IEEE
161views Hardware» more  ISSS 1995»
15 years 1 months ago
Synthesis of pipelined DSP accelerators with dynamic scheduling
To construct complete systems on silicon, application speci c DSP accelerators are needed to speed up the execution of high throughput DSP algorithms. In this paper, a methodology...
Patrick Schaumont, Bart Vanthournout, Ivo Bolsens,...
PACT
2009
Springer
15 years 2 months ago
Parallel Evidence Propagation on Multicore Processors
In this paper, we design and implement an efficient technique for parallel evidence propagation on state-of-the-art multicore processor systems. Evidence propagation is a major ste...
Yinglong Xia, Xiaojun Feng, Viktor K. Prasanna
79
Voted
ISCA
2009
IEEE
138views Hardware» more  ISCA 2009»
15 years 4 months ago
Achieving predictable performance through better memory controller placement in many-core CMPs
In the near term, Moore’s law will continue to provide an increasing number of transistors and therefore an increasing number of on-chip cores. Limited pin bandwidth prevents th...
Dennis Abts, Natalie D. Enright Jerger, John Kim, ...
INFOCOM
2003
IEEE
15 years 2 months ago
Core-stateless Guaranteed Throughput Networks
— End-to-end throughput guarantee is an important service semantics that network providers would like to offer to their customers. A network provider can offer such service seman...
Jasleen Kaur, Harrick M. Vin
GROUP
2009
ACM
15 years 4 months ago
Lazy scheduling of processing and transmission tasks in collaborative systems
A collaborative system must perform both processing and transmission tasks. We present a policy for scheduling these tasks on a single core that is inspired by studies of human pe...
Sasa Junuzovic, Prasun Dewan