141 search results - page 6 / 29 » Core Algorithms of the Maui Scheduler |
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HPDC
2008
IEEE
15 years 4 months ago
2008
IEEE
The emergence of heterogeneous many core architectures presents a unique opportunity for delivering order of magnitude performance increases to high performance applications by ma...
GLVLSI
2002
IEEE
15 years 2 months ago
2002
IEEE
We present a novel test scheduling algorithm for embedded corebased SoC’s. Given a system integrated with a set of cores and a set of test resources, we select a test for each c...
FPL
2003
Springer
15 years 2 months ago
2003
Springer
In this paper we present a single-chip FPGA full encryptor/decryptor core design of the AES algorithm. Our design performs all of them, encryption, decryption and key scheduling pr...
DATE
2006
IEEE
15 years 3 months ago
2006
IEEE
This paper presents a wrapper and test access mechanism design for multi-clock domain SoCs that consists of cores with different clock frequencies during test. We also propose a t...
3DPVT
2004
IEEE
15 years 1 months ago
2004
IEEE
In this paper, we propose a viewer for huge point-sampled models by combining out-of-core technologies with view-dependent level-of-detail (LOD) control. This viewer is designed o...