275 search results - page 54 / 55 » Core architecture optimization for heterogeneous chip multip... |
IPPS
2008
IEEE
14 years 20 days ago
2008
IEEE
High performance computing is critical for financial markets where analysts seek to accelerate complex optimizations such as pricing engines to maintain a competitive edge. In th...
ISPASS
2010
IEEE
14 years 1 months ago
2010
IEEE
—The ongoing move to chip multiprocessors (CMPs) permits greater sharing of last-level cache by processor cores but this sharing aggravates the cache contention problem, potentia...
GLVLSI
1998
IEEE
13 years 10 months ago
1998
IEEE
With the increased clock frequency of modern, high-performance processors over 500 MHz, in some cases, limiting the power dissipation has become the most stringent design target. ...
IEEEPACT
2006
IEEE
14 years 8 days ago
2006
IEEE
As chip multiprocessors (CMPs) become increasingly mainstream, architects have likewise become more interested in how best to share a cache hierarchy among multiple simultaneous t...
HPCA
2008
IEEE
14 years 6 months ago
2008
IEEE
Portable, embedded systems place ever-increasing demands on high-performance, low-power microprocessor design. Dynamic voltage and frequency scaling (DVFS) is a well-known techniq...