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SEMWEB
2010
Springer
14 years 9 months ago
Fusion - Visually Exploring and Eliciting Relationships in Linked Data
Building applications over Linked Data often requires a mapping between the application model and the ontology underlying the source dataset in the Linked Data cloud. This mapping ...
Samur Araújo, Geert-Jan Houben, Daniel Schw...
VTS
2000
IEEE
99views Hardware» more  VTS 2000»
15 years 4 months ago
Virtual Scan Chains: A Means for Reducing Scan Length in Cores
A novel design-for-test (DFT) technique is presented for designing a core with a “virtual scan chain” which looks (to the system integrator) like it is shorter than the real s...
Abhijit Jas, Bahram Pouya, Nur A. Touba
DATE
2000
IEEE
88views Hardware» more  DATE 2000»
15 years 4 months ago
Techniques for Reducing Read Latency of Core Bus Wrappers
Today’s system-on-a-chip designs consist of many cores. To enable cores to be easily integrated into different systems, many propose creating cores with their internal logic sep...
Roman L. Lysecky, Frank Vahid, Tony Givargis
ISLPED
2005
ACM
85views Hardware» more  ISLPED 2005»
15 years 5 months ago
A low-power crossroad switch architecture and its core placement for network-on-chip
As the number of cores on a chip increases, power consumed by the communication structures takes significant portion of the overall power-budget. The individual components of the...
Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen
ICCD
2006
IEEE
185views Hardware» more  ICCD 2006»
15 years 8 months ago
An accurate Energy estimation framework for VLIW Processor Cores
— In this paper, we present a comprehensive energy estimation framework for software executing on Very Long Instruction Word (VLIW) processor cores. The proposed energy model is ...
Sourav Roy, Rajat Bhatia, Ashish Mathur