548 search results - page 1 / 110 » Core-Selectability in Chip Multiprocessors |
77
Voted
IEEEPACT
2009
IEEE
14 years 7 months ago
2009
IEEE
Abstract--The centralized structures necessary for the extraction of instruction-level parallelism (ILP) are consuming progressively smaller portions of the total die area of chip ...
103
Voted
DSN
2011
IEEE
13 years 9 months ago
2011
IEEE
—Aggressive technology scaling causes chip multiprocessors increasingly error-prone. Core-level faulttolerant approaches bind two cores to implement redundant execution and error...
TVLSI
2010
14 years 4 months ago
2010
A new inter-processor communication architecture for chip multiprocessors is proposed which has a low area cost, flexible routing capability, and supports globally asynchronous loc...
NOCS
2010
IEEE
14 years 8 months ago
2010
IEEE
A new asynchronous interconnection network is introduced for globally-asynchronous locally-synchronous (GALS) chip multiprocessors. The network eliminates the need for global cloc...
HPCA
2011
IEEE
14 years 1 months ago
2011
IEEE
Translation Lookaside Buffers (TLBs) are critical to processor performance. Much past research has addressed uniprocessor TLBs, lowering access times and miss rates. However, as c...