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» Core-Selectability in Chip Multiprocessors
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CASES
2006
ACM
15 years 3 months ago
Integrated scratchpad memory optimization and task scheduling for MPSoC architectures
Multiprocessor system-on-chip (MPSoC) is an integrated circuit containing multiple instruction-set processors on a single chip that implements most of the functionality of a compl...
Vivy Suhendra, Chandrashekar Raghavan, Tulika Mitr...
ICPP
2005
IEEE
15 years 3 months ago
Exploring Processor Design Options for Java-Based Middleware
Java-based middleware is a rapidly growing workload for high-end server processors, particularly Chip Multiprocessors (CMP). To help architects design future microprocessors to ru...
Martin Karlsson, Erik Hagersten, Kevin E. Moore, D...
IPPS
2005
IEEE
15 years 3 months ago
Predicting Cache Space Contention in Utility Computing Servers
The need to provide performance guarantee in high performance servers has long been neglected. Providing performance guarantee in current and future servers is difficult because ļ...
Yan Solihin, Fei Guo, Seongbeom Kim
ISCA
2005
IEEE
119views Hardware» more  ISCA 2005»
15 years 3 months ago
Rescue: A Microarchitecture for Testability and Defect Tolerance
Scaling feature size improves processor performance but increases each device’s susceptibility to defects (i.e., hard errors). As a result, fabrication technology must improve s...
Ethan Schuchman, T. N. Vijaykumar
83
Voted
MICRO
2005
IEEE
163views Hardware» more  MICRO 2005»
15 years 3 months ago
ReSlice: Selective Re-Execution of Long-Retired Misspeculated Instructions Using Forward Slicing
As more data value speculation mechanisms are being proposed to speed-up processors, there is growing pressure on the critical processor structures that must buffer the state of t...
Smruti R. Sarangi, Wei Liu, Yuanyuan Zhou