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» Core-Selectability in Chip Multiprocessors
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HPCA
2007
IEEE
15 years 6 months ago
An Adaptive Shared/Private NUCA Cache Partitioning Scheme for Chip Multiprocessors
The significant speed-gap between processor and memory and the limited chip memory bandwidth make last-level cache performance crucial for future chip multiprocessors. To use the...
Haakon Dybdahl, Per Stenström
ICCAD
2008
IEEE
97views Hardware» more  ICCAD 2008»
15 years 8 months ago
Integrated code and data placement in two-dimensional mesh based chip multiprocessors
— As transistor sizes continue to shrink and the number of transistors per chip keeps increasing, chip multiprocessors (CMPs) are becoming a promising alternative to remain on th...
Taylan Yemliha, Shekhar Srikantaiah, Mahmut T. Kan...
95
Voted
ASPLOS
2008
ACM
15 years 1 months ago
Exploiting access semantics and program behavior to reduce snoop power in chip multiprocessors
Integrating more processor cores on-die has become the unanimous trend in the microprocessor industry. Most of the current research thrusts using chip multiprocessors (CMPs) as th...
Chinnakrishnan S. Ballapuram, Ahmad Sharif, Hsien-...
MICRO
2008
IEEE
137views Hardware» more  MICRO 2008»
14 years 11 months ago
Verification of chip multiprocessor memory systems using a relaxed scoreboard
Verification of chip multiprocessor memory systems remains challenging. While formal methods have been used to validate protocols, simulation is still the dominant method used to ...
Ofer Shacham, Megan Wachs, Alex Solomatnikov, Amin...
VLSID
2009
IEEE
144views VLSI» more  VLSID 2009»
16 years 10 days ago
Exploring Carbon Nanotube Bundle Global Interconnects for Chip Multiprocessor Applications
The current paradigm of using Cu interconnects for on-chip global communication is rapidly becoming a serious performance bottleneck in ultra-deep submicron (UDSM) technologies. C...
Sudeep Pasricha, Nikil Dutt, Fadi J. Kurdahi