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» Core-Selectability in Chip Multiprocessors
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PPOPP
1990
ACM
15 years 8 months ago
Employing Register Channels for the Exploitation of Instruction Level Parallelism
Abstract - A multiprocessor system capable of exploiting fine-grained parallelism must support efficient synchronization and data passing mechanisms. This paper demonstrates the us...
Rajiv Gupta
ASPLOS
2009
ACM
16 years 4 months ago
Accelerating critical section execution with asymmetric multi-core architectures
To improve the performance of a single application on Chip Multiprocessors (CMPs), the application must be split into threads which execute concurrently on multiple cores. In mult...
M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi...
ICPP
2009
IEEE
15 years 10 months ago
Accelerating Lattice Boltzmann Fluid Flow Simulations Using Graphics Processors
—Lattice Boltzmann Methods (LBM) are used for the computational simulation of Newtonian fluid dynamics. LBM-based simulations are readily parallelizable; they have been implemen...
Peter Bailey, Joe Myre, Stuart D. C. Walsh, David ...
IEEEPACT
2008
IEEE
15 years 10 months ago
The PARSEC benchmark suite: characterization and architectural implications
This paper presents and characterizes the Princeton Application Repository for Shared-Memory Computers (PARSEC), a benchmark suite for studies of Chip-Multiprocessors (CMPs). Prev...
Christian Bienia, Sanjeev Kumar, Jaswinder Pal Sin...
APPT
2007
Springer
15 years 10 months ago
Replication-Based Partial Dynamic Scheduling on Heterogeneous Network Processors
It is a great challenge to map network processing tasks to processing resources of advanced network processors, which are heterogeneous and multi-threading multiprocessor System-on...
Zhiyong Yu, Zhiyi Yang, Fan Zhang, Zhiwen Yu, Tuan...