548 search results - page 75 / 110 » Core-Selectability in Chip Multiprocessors |
128
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IEEEPACT
2009
IEEE
15 years 10 months ago
2009
IEEE
— This research demonstrates that coming support for hardware transactional memory can be leveraged to significantly reduce the cost of implementing true speculative multithread...
105
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DEBS
2009
ACM
15 years 10 months ago
2009
ACM
Event processing systems are a promising technology for enterprise-scale applications. However, achieving scalability yet maintaining high performance is a challenging problem. Th...
131
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ISCAS
2008
IEEE
15 years 10 months ago
2008
IEEE
Abstract— This paper presents circuits that enable dynamic voltage and frequency scaling (DVFS) for finegrained chip multi-processors to reduce both dynamic and leakage power di...
140
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DDECS
2006
IEEE
15 years 10 months ago
2006
IEEE
—The impact of shared instruction memory on performance is measured and analyzed for an FPGAbased Multiprocessor System-on-Chip (MP-SoC) with an MPEG-4 video encoding application...
138
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DATE
2005
IEEE
15 years 9 months ago
2005
IEEE
With the advent of multi-processor systems on a chip, the interest for message passing libraries has revived. Message passing helps in mastering the design complexity of parallel ...