548 search results - page 78 / 110 » Core-Selectability in Chip Multiprocessors |
240
Voted
APSCC
2010
IEEE
15 years 2 months ago
2010
IEEE
Middleware for web service orchestration, such as runtime engines for executing business processes, workflows, or web service compositions, can easily become performance bottleneck...
266
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GLVLSI
2011
IEEE
14 years 7 months ago
2011
IEEE
This paper proposes a novel L1 data cache design with dualversioning SRAM cells (dvSRAM) for chip multi-processors (CMP) that implement optimistic concurrency proposals. In this n...
140
Voted
ISCA
2011
IEEE
14 years 7 months ago
2011
IEEE
Network-on-chip (NoC) has become a critical shared resource in the emerging Chip Multiprocessor (CMP) era. Most prior NoC designs have used the same type of router across the enti...
174
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ISCA
2011
IEEE
14 years 7 months ago
2011
IEEE
Today’s chip-level multiprocessors (CMPs) feature up to a hundred discrete cores, and with increasing levels of integration, CMPs with hundreds of cores, cache tiles, and specia...
173
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ASAP
2011
IEEE
14 years 4 months ago
2011
IEEE
—The domain of vision and navigation often includes applications for feature tracking as well as simultaneous localization and mapping (SLAM). As these problems require computati...