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» Core-Selectability in Chip Multiprocessors
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DATE
2003
IEEE
176views Hardware» more  DATE 2003»
15 years 9 months ago
Hardware/Software Partitioning of Operating Systems
As MultiProcessor System-on-a-Chip (MPSoC) designs become more common, hardware/software codesign engineers face new challenges involving operating system integration. To speed up...
Vincent John Mooney
GECCO
2010
Springer
233views Optimization» more  GECCO 2010»
15 years 8 months ago
Evolutionary-based conflict-free scheduling of collective communications on spidergon NoCs
The Spidergon interconnection network has become popular recently in multiprocessor systems on chips. To the best of our knowledge, algorithms for collective communications (CC) h...
Jirí Jaros, Vaclav Dvorak
EUROPAR
2006
Springer
15 years 7 months ago
PAM-SoC: A Toolchain for Predicting MPSoC Performance
In the past, research on Multiprocessor Systems-on-Chip (MPSoC) has focused mainly on increasing the available processing power on a chip, while less effort was put into specific s...
Ana Lucia Varbanescu, Henk J. Sips, Arjan J. C. va...
ASPDAC
2009
ACM
115views Hardware» more  ASPDAC 2009»
15 years 1 months ago
Frequent value compression in packet-based NoC architectures
The proliferation of Chip Multiprocessors (CMPs) has led to the integration of large on-chip caches. For scalability reasons, a large on-chip cache is often divided into smaller ba...
Ping Zhou, Bo Zhao, Yu Du, Yi Xu, Youtao Zhang, Ju...
ISCA
2009
IEEE
189views Hardware» more  ISCA 2009»
15 years 10 months ago
Hybrid cache architecture with disparate memory technologies
Caching techniques have been an efficient mechanism for mitigating the effects of the processor-memory speed gap. Traditional multi-level SRAM-based cache hierarchies, especially...
Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Ra...