Sciweavers

548 search results - page 84 / 110
» Core-Selectability in Chip Multiprocessors
Sort
View
ISPASS
2010
IEEE
15 years 10 months ago
Hardware prediction of OS run-length for fine-grained resource customization
—In the past ten years, computer architecture has seen a paradigm shift from emphasizing single thread performance to energy efficient, throughput oriented, chip multiprocessors...
David Nellans, Kshitij Sudan, Rajeev Balasubramoni...
122
Voted
ISQED
2009
IEEE
136views Hardware» more  ISQED 2009»
15 years 10 months ago
NBTI aware workload balancing in multi-core systems
—As device feature size continues to shrink, reliability becomes a severe issue due to process variation, particle-induced transient errors, and transistor wear-out/stress such a...
Jin Sun, Avinash Karanth Kodi, Ahmed Louri, Janet ...
SC
2009
ACM
15 years 10 months ago
Future scaling of processor-memory interfaces
Continuous evolution in process technology brings energyefficiency and reliability challenges, which are harder for memory system designs since chip multiprocessors demand high ba...
Jung Ho Ahn, Norman P. Jouppi, Christos Kozyrakis,...
DATE
2009
IEEE
128views Hardware» more  DATE 2009»
15 years 10 months ago
Temperature-aware scheduler based on thermal behavior grouping in multicore systems
—Dynamic Thermal Management techniques have been widely accepted as a thermal solution for their low cost and simplicity. The techniques have been used to manage the heat dissipa...
Inchoon Yeo, Eun Jung Kim
IISWC
2009
IEEE
15 years 10 months ago
Understanding PARSEC performance on contemporary CMPs
PARSEC is a reference application suite used in industry and academia to assess new Chip Multiprocessor (CMP) designs. No investigation to date has profiled PARSEC on real hardwa...
Major Bhadauria, Vincent M. Weaver, Sally A. McKee