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» Core-Selectability in Chip Multiprocessors
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MICRO
2007
IEEE
141views Hardware» more  MICRO 2007»
15 years 10 months ago
Composable Lightweight Processors
Modern chip multiprocessors (CMPs) are designed to exploit both instruction-level parallelism (ILP) within processors and thread-level parallelism (TLP) within and across processo...
Changkyu Kim, Simha Sethumadhavan, M. S. Govindan,...
MICRO
2007
IEEE
188views Hardware» more  MICRO 2007»
15 years 10 months ago
Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding
In deep sub-micron ICs, growing amounts of ondie memory and scaling effects make embedded memories increasingly vulnerable to reliability and yield problems. As scaling progresses...
Jangwoo Kim, Nikos Hardavellas, Ken Mai, Babak Fal...
RTCSA
2007
IEEE
15 years 10 months ago
An MPSoC Performance Estimation Framework Using Transaction Level Modeling
— To use the tremendous hardware resources available in next generation MultiProcessor Systems-on-Chip (MPSoC) efficiently, rapid and accurate design space exploration (DSE) met...
Rabie Ben Atitallah, Smaïl Niar, Samy Meftali...
CP
2007
Springer
15 years 10 months ago
Scheduling Conditional Task Graphs
The increasing levels of system integration in Multi-Processor System-on-Chips (MPSoCs) emphasize the need for new design flows for efficient mapping of multi-task applications o...
Michele Lombardi, Michela Milano
129
Voted
VLDB
2007
ACM
166views Database» more  VLDB 2007»
15 years 10 months ago
To Share or Not To Share?
Intuitively, aggressive work sharing among concurrent queries in a database system should always improve performance by eliminating redundant computation or data accesses. We show...
Ryan Johnson, Nikos Hardavellas, Ippokratis Pandis...