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» Core-Selectability in Chip Multiprocessors
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ICDM
2006
IEEE
147views Data Mining» more  ICDM 2006»
15 years 10 months ago
Adaptive Parallel Graph Mining for CMP Architectures
Mining graph data is an increasingly popular challenge, which has practical applications in many areas, including molecular substructure discovery, web link analysis, fraud detect...
Gregory Buehrer, Srinivasan Parthasarathy, Yen-Kua...
IPPS
2006
IEEE
15 years 10 months ago
Coterminous locality and coterminous group data prefetching on chip-multiprocessors
Due to shared cache contentions and interconnect delays, data prefetching is more critical in alleviating penalties from increasing memory latencies and demands on Chip-Multiproce...
Xudong Shi, Zhen Yang, Jih-Kwon Peir, Lu Peng, Yen...
IPPS
2006
IEEE
15 years 10 months ago
Reducing the associativity and size of step caches in CRCW operation
Step caches are caches in which data entered to an cache array is kept valid only until the end of ongoing step of execution. Together with an advanced pipelined multithreaded arc...
M. Forsell
ISCA
2006
IEEE
138views Hardware» more  ISCA 2006»
15 years 10 months ago
Program Demultiplexing: Data-flow based Speculative Parallelization of Methods in Sequential Programs
We present Program Demultiplexing (PD), an execution paradigm that creates concurrency in sequential programs by "demultiplexing" methods (functions or subroutines). Cal...
Saisanthosh Balakrishnan, Gurindar S. Sohi
ISCAS
2006
IEEE
87views Hardware» more  ISCAS 2006»
15 years 10 months ago
NoC monitoring: impact on the design flow
Abstract— Networks-on-chip (NoCs) are a scalable interconnect solution to large scale multiprocessor systems on chip and are rapidly becoming reality. As the ratio of embedded co...
Calin Ciordas, Kees Goossens, Andrei Radulescu, Tw...