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» Core-Selectability in Chip Multiprocessors
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121
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ISQED
2006
IEEE
101views Hardware» more  ISQED 2006»
15 years 10 months ago
Compiler-Directed Power Density Reduction in NoC-Based Multi-Core Designs
As transistor counts keep increasing and clock frequencies rise, high power consumption is becoming one of the most important obstacles, preventing further scaling and performance...
Sri Hari Krishna Narayanan, Mahmut T. Kandemir, Oz...
134
Voted
ASPLOS
2006
ACM
15 years 10 months ago
SecCMP: a secure chip-multiprocessor architecture
Security has been considered as an important issue in processor design. Most of the existing mechanisms address security and integrity issues caused by untrusted main memory in si...
Li Yang, Lu Peng
ISLPED
2006
ACM
105views Hardware» more  ISLPED 2006»
15 years 10 months ago
Reducing power through compiler-directed barrier synchronization elimination
Interprocessor synchronization, while extremely important for ensuring execution correctness, can be very costly in terms of both power and performance overheads. Unfortunately, m...
Mahmut T. Kandemir, Seung Woo Son
IEEEPACT
2005
IEEE
15 years 9 months ago
Maximizing CMP Throughput with Mediocre Cores
In this paper we compare the performance of area equivalent small, medium, and large-scale multithreaded chip multiprocessors (CMTs) using throughput-oriented applications. We use...
John D. Davis, James Laudon, Kunle Olukotun
HIPEAC
2005
Springer
15 years 9 months ago
Enhancing Network Processor Simulation Speed with Statistical Input Sampling
Abstract. While cycle-accurate simulation tools have been widely used in modeling high-performance processors, such an approach can be hindered by the increasing complexity of the ...
Jia Yu, Jun Yang 0002, Shaojie Chen, Yan Luo, Laxm...