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» Core-Selectability in Chip Multiprocessors
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ICS
2005
Tsinghua U.
15 years 9 months ago
A NUCA substrate for flexible CMP cache sharing
We propose an organization for the on-chip memory system of a chip multiprocessor, in which 16 processors share a 16MB pool of 256 L2 cache banks. The L2 cache is organized as a n...
Jaehyuk Huh, Changkyu Kim, Hazim Shafi, Lixin Zhan...
HIPC
2004
Springer
15 years 9 months ago
Parallel Performance of Hierarchical Multipole Algorithms for Inductance Extraction
Parasitic extraction techniques are used to estimate signal delay in VLSI chips. Inductance extraction is a critical component of the parasitic extraction process in which on-chip ...
Hemant Mahawar, Vivek Sarin, Ananth Grama
ISLPED
2009
ACM
123views Hardware» more  ISLPED 2009»
15 years 8 months ago
Predict and act: dynamic thermal management for multi-core processors
In this paper, we propose a proactive dynamic thermal management scheme for chip multiprocessors that run multi-threaded workloads. We introduce a new predictor that utilizes the ...
Raid Zuhair Ayoub, Tajana Simunic Rosing
ISCA
2000
IEEE
90views Hardware» more  ISCA 2000»
15 years 8 months ago
A scalable approach to thread-level speculation
While architects understandhow to build cost-effective parallel machines across a wide spectrum of machine sizes (ranging from within a single chip to large-scale servers), the re...
J. Gregory Steffan, Christopher B. Colohan, Antoni...
ASPLOS
2000
ACM
15 years 8 months ago
Slipstream Processors: Improving both Performance and Fault Tolerance
Processors execute the full dynamic instruction stream to arrive at the final output of a program, yet there exist shorter instruction streams that produce the same overall effec...
Karthik Sundaramoorthy, Zachary Purser, Eric Roten...