548 search results - page 9 / 110 » Core-Selectability in Chip Multiprocessors |
ISQED
2010
IEEE
14 years 11 months ago
2010
IEEE
- In a multi-core system, power and performance may be dynamically traded off by utilizing power management (PM). This paper addresses the problem of minimizing the total power con...
68
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JSA
2007
14 years 9 months ago
2007
This paper presents a scalable and partitionable asynchronous bus arbiter for use with chip multiprocessors (CMP) and its corresponding pre-layout simulation results using VHDL. T...
ASPDAC
2007
ACM
15 years 1 months ago
2007
ACM
Abstract--An integrated test scheduling methodology for multiprocessor System-on-Chips (SOC) utilizing the functional buses for test data delivery is described. The proposed method...
DATE
2004
IEEE
15 years 1 months ago
2004
IEEE
This work focuses on communication architecture analysis for multi-processor Systems-on-Chips (MPSoCs), and it leverages a SystemC-based platform to simulate a complete multi-proc...
102
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TPDS
2008
14 years 9 months ago
2008
It is widely accepted that transient failures will appear more frequently in chips designed in the near future due to several factors such as the increased integration scale. On th...