92 search results - page 16 / 19 » Correct-by-construction microarchitectural pipelining |
ISCA
1998
IEEE
15 years 1 months ago
1998
IEEE
Control-flow misprediction penalties are a major impediment to high performance in wide-issue superscalar processors. In this paper we present Selective Eager Execution (SEE), an ...
FPL
2007
Springer
15 years 1 months ago
2007
Springer
: Molecular dynamics simulation based on discrete event simulation (DMD) is emerging as an alternative to time-step driven molecular dynamics (MD). DMD uses simplified discretized ...
CGO
2004
IEEE
15 years 1 months ago
2004
IEEE
Instruction scheduling hardware can be simplified and easily pipelined if pairs of dependent instructions are fused so they share a single instruction scheduling slot. We study an...
MAM
2008
14 years 9 months ago
2008
Designing high-performance low-energy register files is of critical importance to the continuation of current performance advances in wide-issue and deeply pipelined superscalar m...
ISCA
2002
IEEE
15 years 2 months ago
2002
IEEE
This paper presents the Alpha EV8 conditional branch predictor. The Alpha EV8 microprocessor project, canceled in June 2001 in a late phase of development, envisioned an aggressiv...