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121
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DATE
2006
IEEE
152views Hardware» more  DATE 2006»
15 years 9 months ago
Adaptive chip-package thermal analysis for synthesis and design
Ever-increasing integrated circuit (IC) power densities and peak temperatures threaten reliability, performance, and economical cooling. To address these challenges, thermal analy...
Yonghong Yang, Zhenyu (Peter) Gu, Changyun Zhu, Li...
120
Voted
RTSS
2008
IEEE
15 years 10 months ago
Merging State and Preserving Timing Anomalies in Pipelines of High-End Processors
Many embedded systems are subject to temporal constraints that require advance guarantees on meeting deadlines. Such systems rely on static analysis to safely bound worst-case exe...
Sibin Mohan, Frank Mueller
111
Voted
ETS
2007
IEEE
94views Hardware» more  ETS 2007»
15 years 10 months ago
An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy
An efficient on-chip infrastructure for memory test and repair is crucial to enhance yield and availability of SoCs. Therefore embedded memories are commonly equipped with spare r...
Philipp Öhler, Sybille Hellebrand, Hans-Joach...
133
Voted
MEMOCODE
2003
IEEE
15 years 9 months ago
MoDe: A Method for System-Level Architecture Evaluation
System-level design methodologies for embedded HW/SW systems face several challenges: In order to be susceptible to systematic formal analysis based on state-space exploration, a ...
Jan Romberg, Oscar Slotosch, Gabor Hahn
137
Voted
DATE
2008
IEEE
163views Hardware» more  DATE 2008»
15 years 5 months ago
A Simulation Methodology for Worst-Case Response Time Estimation of Distributed Real-Time Systems
In this paper, we propose a simulation-based methodology for worst-case response time estimation of distributed realtime systems. Schedulability analysis produces pessimistic uppe...
Soheil Samii, Sergiu Rafiliu, Petru Eles, Zebo Pen...